Evaluation of capacitance-voltage characteristics for high voltage SiC-JFET

Capacitance between terminals of a power semiconductor device substantially affects on its switching operation. This paper presents a capacitance–voltage (C–V) characterization system for measuring high voltage SiC–JFET and the results. The C–V characterization system enables one to impose high drain-source voltage to the device and extracts the capacitance between two of three terminals in FET by eliminating its influence on the neighboring terminal. The capacitance between the gate and drain, and the drain and source represents the hybrid structure of the lateral channel and vertical drift layer of the SiC–JFET.